This invention relates to single transistor frequency multiplier circuits. More specifically, this invention relates to single-transistor frequency doublers.
A frequency doubler is a circuit that produces an output signal, (usually a sinusoidal but also possibly including square waves, sawtooth waves, etc.) at twice the frequency of an input signal. Input signal is suppressed from the output.
Ideally, a frequency doubler can double any input frequency, f.sub.in, but in reality has a bandwidth defined as the difference between the range of permissible input frequencies, i.e., f.sub.0 -f.sub.1 divided by f.sub.1, (where f.sub.1 is the highest input frequency that the doubler can accept and f.sub.0 is the lowest frequency the doubler accepts). For a range of input frequencies f.sub.in =f.sub.0 to f.sub.1, as f.sub.1 gets larger, it eventually equals the value of 2f.sub.0, the doubled, lower input frequency f.sub.0. Input signals (f.sub.in) in the range beyond f.sub.0 -f.sub.1 cannot be doubled by the circuit because the circuit cannot double f.sub.0 to produce 2f.sub.0 signals, yet suppress from the output, f.sub.1 input signals nearly equal to 2f.sub.0.
The mathematical limit of the bandwidth of a frequency doubler is fifty percent. For example, a frequency doubler capable of accepting an input frequency between 100 and 150 MHz that produces an output frequency between 200 and 300 MHz, has a bandwidth of 33%. A frequency doubler with an input frequency between 100 and 200 MHz and an output frequency of 200 to 400 MHz has a bandwidth of 50% where 2f.sub.0 equals f.sub.1. In reality because of physical limitations of circuit components, prior art single transistor doublers typically have bandwidths around fifteen percent.
Prior art single transistor doublers typically have narrow bandwidths because of the characteristics of traps and filters used to suppress undesired frequencies at the output of the doubler. A single transistor frequency doubler typically consists of a base circuit trap resonant at 2f.sub.in and a combination of collector circuit traps and filters designed to suppress f.sub.in signal yet pass 2f.sub.in signals. To suppress f.sub.in signals from the output prior art traps and filters substantially limit the bandwidth of frequency doublers.
Increasing the bandwidth of a frequency doubler can usually be had only at the expense of additional transistor stages or additional passive circuitry in the base or collector circuits adding to parts count and signal losses and also increasing the complexity of the circuit. A frequency doubler having a wider bandwidth without substantially increasing the parts count would improve the performance and reduce the cost of a radio requiring these types of circuits.